A new kind of transmission system in which a plurality of signal channels are multiplexed with some phase difference is considered as a subscriber transmission system in an Integrated Service Digital Network (ISDN). In the ISDN transmission system, a bus line system between a digital service unit as a master station and a terminal apparatus as a slave station is considered promising in the number of necessary lines, the simple process for expanding, and less quantity of necessary hardware.
FIG. 1 shows a subscriber coupling system with a bus line schematically. In the figure, the numeral 1 is a digital service unit (DSU), 2-1 through 2-N are n number of terminal apparatuses, 3 is a T line (transmission line), 4 is an R line (reception line), 5 is a termination circuit. As shown, a plurality of terminal apparatuses are coupled with one another in a bus line. The T line and the R line show bus lines, and the R line is directed from the DSU to each terminal apparatuses, and the T line is directed from each terminal apparatuses to the DSU.
In a bus system for subscriber system, a simple bus system as shown in FIG. 2A (length between DSU and DT.sub.1 is 0, and the length between DT.sub.1 and DT.sub.n is about 100 m), an extended bus system as shown in FIG. 2B (the length between DSU and DT.sub.1 is about 500 m, and the length between DT.sub.1 and DT.sub.n is about 30 m), and a point-to-point system as shown in FIG. 2C (length between DSU and DT.sub.1 is longer than 1000 m) are three typical ones. In FIGS. 2A through 2C, the same reference numerals as those of FIG. 1 show the same members.
The phase lock operation between a transmission side and a reception side in FIGS. 2A through 2C has been carried out as described below.
The DSU transmits a data to an R line like a broadcasting manner, and each subscriber apparatus derives clock component in reception data train for phase lock purposes. However, the reception phase at the DSU through the T line is not uniform, because the length between the DSU and each terminal apparatus differs for each terminal apparatus. Of course, it is preferable that a common DSU is used for the systems of FIGS. 2A through 2C. Accordingly, a 100% AMI code is used as a transmission code, and each terminal apparatus transmits not only an information data but also a frame bit which indicates the beginning of a frame, so that the DSU may derive a sampling clock by a conventional phase lock circuit.
FIG. 3 shows the configuration of a prior digital phase lock circuit. In the figure, the numeral 6 is a binary level quantized phase comparator, 7 is a sequential loop filter, 8 is a fixed oscillator, 9 is a circuit for pulse add and/or pulse delete, and 10 is a frequency divider. In FIG. 3, the phase comparator 6 compares the phase of an input signal with the output signal phase for every input bit, and provides output as +1 or -1, which is applied to the sequential loop filter 7 for improving the control reliability to control the circuit 9. The sequential loop filter 7 is usually composed of an up/down counter which is incremented by +1 input signal and is decremented by -1 input signal. The up/down counter provides an output signal when the content of the up/down counter reaches the predetermined value N or 0 (zero). The circuit 9 inserts a pulse to the output signal of the fixed oscillator 8, or removes a pulse from the output signal, according to the output of the up/down counter. The output of the circuit 9 is applied to the divider 10 which divides the pulses to provide a phased locked output signal.
FIG. 4 shows a prior phase lock system in a DSU unit having a prior phase lock circuit of FIG. 3. In the figure, FIG. 4A shows the configuration of the coupling, and the same reference numerals as those of FIG. 1 shows the same member, DT.sub.0 is the closest terminal apparatus to the DSU, DT.sub.L is the farthest terminal apparatus from the DSU, and DT.sub.M is a terminal apparatus located between DT.sub.0 and DT.sub.L. FIG. 4B shows the time sequence of the signals in FIG. 3.
It is assumed that the length between DSU and DT.sub.0 is 0, and the length between DSU and DT.sub.M is 0, and the length between DSU and DT.sub.L is l.sub.m. Also, the frame structure of FIG. 5 is assumed. In the embodiment, each frame has 24 bits in 125 micro seconds, and the transmission speed is 192 kbps. In the figure, B.sub.1 and B.sub.2 are channels of 64 kbps, D is a channel of 16 kbps, F is a frame bit for indicating the head of the frame, G is a guard bit, and S is a spare bit. The guard bit G is transmitted as a high impedance mode of a driver in a transmission side. The frame structure using the 100% duty AMI code is shown in FIG. 5(b). Each individual channel is DC-balanced by a trailing balance bit. The terminal apparatuses DT.sub.0 and DT.sub.M are designated the time slots B.sub.1, and B.sub.2, respectively, and the terminal apparatus DT.sub.L is designated the time slot D. When the DSU sends a data which is generated by the clock CLK.sub.1 with the period T.sub.0 to the R line with the phase (1) as shown in FIG. 4B, the data phases (2) and (3) at the input ends A and B of the terminal apparatuses DT.sub.0 and DT.sub.M are equal to the phase (1), and the data phase (4) at the input C of the terminal apparatus DT.sub.L is delayed by t.sub.0 from the phase (1). When the transmission delay of a cable is v(sec/m), the figure t.sub.0 is expressed as t.sub.0 =v.times.t (sec). The data transmission phase in each terminal apparatus to the T line is adjusted so that the transmission phase coincides with the reception phase in the R line. Accordingly, the transmission phase (5) in the terminal apparatus DT.sub.L is equal to the phase (4), the transmission phase (6) in the terminal apparatus DT.sub.M is equal to the reception phase (3), and the transmission phase (7) in the terminal apparatus DT.sub.0 is equal to the reception phase (2). However, the reception phase at the DSU depends upon the location of each terminal apparatus, and the data phase (8).sub.L from the terminal apparatus DT.sub.L delayed by 2t.sub.0 from the data phase (1), and the data phase (8).sub.0 from the terminal apparatuses DT.sub.0 and DT.sub.M is almost the same as the data phase (1). In that case, the number of bits arrived at DSU with the data phase (8).sub.L is 8 times (=2.times.(64/16)) as many as those bits with the data phase (8).sub.0. In that case, the output phase-locked signal obtained by the circuit of FIG. 3 dependes mostly upon the data phase (8).sub.0 which has 8 times as many bits as that of data phase (8).sub.L, and the phase-locked clock CLK.sub.2 is obtained.
Considering that the retiming margin is larger than 1/4 time slot (=0.25 T.sub.0) for the deterioration of waveforms in a transmission line, the following equation must be satisfied so that the margin is provided to the data phase (8).sub.L. EQU 2t.sub.0 &lt;0.25T.sub.0 ( 1)
As an ordinary cable has v=5 (nsec/m), and the transmission rate is 192 kbps, t.sub.0 &lt;650 (nsec) is derived from the equation (1), and the allowable maximum length for correct reception is shown by the following equation. EQU L&lt;t.sub.0 /v=130 (m) (2)
As shown in the equation (2), the length to a subscriber is severely limited in a prior art. That limitation is the serious disadvantage when an ISDN system is applied to a wide area of offices.
Further, a prior art has the disadvantage the margin of a sampling clock is small for the data phase (8).sub.L, and the error rate of that signal is deteriorated.